Last updated: Sat Jul 31 18:04:17 CEST 2010
References and code
| Cache Mechanism | Code | |
|---|---|---|
| [1, NULL] | Bus, code in Bus.sim NULL | Bus.sim Bus.h |
| [2, NULL] | Dram, code in DRAM.sim NULL | DRAM.sim DRAM.h |
| [3, NULL] | Blocking Cache, code in CacheWB.sim Blocking Write Back Cache, 1980. | CacheWB.sim |
| [4, NULL] | PowerPC405, code in CpuPPC405.sim NULL | CpuPPC405.sim CpuPPC405.h |
| [5, Cooksey et al.] | Content-Directed Prefetcher, code in CacheWBNBCDP.sim Robert Cooksey, Stephan Jourdan and Dirk Grunwald: A stateless, content-directed data prefetching mechanism, ASPLOS 2002. | CacheWBNBCDP.sim CacheWBNBCDP.h |
| [6, NULL] | NULL, code in .sim NULL | .sim .h |
| [7, Smith] | Tag Prefetcher, code in CacheWBNBTP.sim Alan Jay Smith: Cache Memories, ACM Computing Surveys, 1982. | CacheWBNBTP.sim CacheWBNBTP.h |
| [8, Nesbit et al.] | Stride Prefetcher, code in CacheWBNBSP.sim Kyle J. Nesbit and James E. Smith: Data Cache Prefetching Using a Global History Buffer, HPCA 2004. | CacheWBNBSP.sim CacheWBNBSP.h |
| [9, Nesbit et al.] | Global History Prefetcher, code in CacheWBNBGHB.sim Kyle J. Nesbit and James E. Smith: Data Cache Prefetching Using a Global History Buffer, HPCA 2004. | CacheWBNBGHB.sim CacheWBNBGHB.h |
| [10, NULL] | Non-blocking Cache, code in CacheWBNB.sim Non-Blocking Write Back Cache, 1980. | CacheWBNB.sim CacheWBNB.h |
| [11, Hu et al.] | Timekeeping Victim Cache, code in CacheWBNBVCTKMultiPorted.sim Zhigang Hu, Stefanos Kaxiras and Margaret Martonosi: Timekeeping in the memory system: predicting and optimizing memory behavior, ISCA 2002. | CacheWBNBVCTKMultiPorted.sim CacheWBNBVCTKMultiPorted.h |
| [12, Cooksey et al.] | Stride + Content-Directed Prefetcher, code in CacheWBNBCDPSP.sim Robert Cooksey, Stephan Jourdan and Dirk Grunwald: A stateless, content-directed data prefetching mechanism, ASPLOS 2002. | CacheWBNBCDPSP.sim CacheWBNBCDPSP.h |
| [13, Jouppi] | Victim Cache, code in CacheWBNBVCMultiPorted.sim Norman P. Jouppi: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, ISCA 1990. | CacheWBNBVCMultiPorted.sim CacheWBNBVCMultiPorted.h |
| [14, NULL] | NULL, code in BusMultiQueue.sim NULL | BusMultiQueue.sim BusMultiQueue.h |
| [15, NULL] | NULL, code in BusMultiQueue.sim NULL | BusMultiQueue.sim BusMultiQueue.h |
| [16, NULL] | NULL, code in Pipeliner.sim NULL | Pipeliner.sim Pipeliner.h |
| [17, NULL] | NULL, code in [1;33m03:14:08[0m.sim NULL | [1;33m03:14:08[0m.sim [1;33m03:14:08[0m.h |
| [20, NULL] | NULL, code in NewModule.sim NULL | NewModule.sim NewModule.h |
| [21, Seznec] | Blocking Skewed Associative Cache, code by Nathanaël Prémillieu and André Seznec in CacheWBSKEW.sim André Seznec: A Case for Two-Way Skewed-Associative Caches, ISCA 1993. | CacheWBSKEW.sim |
| [22, NULL] | NULL, code in Pipeliner.sim NULL | Pipeliner.sim Pipeliner.h |
| [23, Seznec] | Non-blocking Skewed Associative Cache, code by Nathanaël Prémillieu and André Seznec in CacheWBNBSKEW.sim André Seznec: A Case for Two-Way Skewed-Associative Caches, ISCA 1993. | CacheWBNBSKEW.sim CacheWBNBSKEW.h |
| [24, NULL] | New Cache, code in CacheVeerle.sim NULL | CacheVeerle.sim CacheVeerle.h |
| [25, NULL] | Tested Cache, code in TESTCache.sim NULL | TESTCache.sim TESTCache.h |
| [26, Grannæs et al.] | Delta Correlating Prediction Tables, code by Marius Grannæs, Magnus Jahre, and Lasse Natvig in CacheWBNBDCPT.sim Storage Efficient Hardware Prefetching using Delta Correlating Prediction Tables, Finalist in the 1st Data Prefetching Competition (DPC) held in conjunction with HPCA 2009. | CacheWBNBDCPT.sim CacheWBNBDCPT.h |
| [27, ] | , code by in SecondTest.sim | SecondTest.sim |
| [28, ] | , code by in DemoTest.sim | DemoTest.sim |
| [29, ] | , code by in UploadTest.sim | UploadTest.sim |
| [30, ] | Test1700, code by in Test1700.sim | Test1700.sim |
| [31, ] | DemoTuesday, code by in DemoTuesday.sim | DemoTuesday.sim |