/********************************* 
  Details for configuration 21441
 ********************************* 
 Module bus_multiqueue.sim
	nCPU	2
	nBufferSize	10
	nRequestWidth	128
	Snooping	false
 Module dram.sim
	nBanks	2
	nRows	2048
	nCols	1024
	TRRD	60
	TRAS	150
	TRCD	60
	CL	60
	TRP	60
	TRC	210
	TREF	10000000
	nDataPathSize	128
	nCacheLineSize	128
	nCtrlQueueSize	8
	nProg	1
	Snooping	false
	VERBOSE	false
 Module CacheWBNBTP.sim
	nCPUtoCacheDataPathSize	8
	nCachetoCPUDataPathSize	8
	nMemtoCacheDataPathSize	128
	nCachetoMemDataPathSize	128
	nLineSize	128
	nCacheLines	65536
	nAssociativity	1
	nStages	1
	nDelay	1
	nProg	1
	nMSHR	8
	nMSHRRead	64
	nPrefetchQueue	16
 Module CpuPPC405.sim
	nIntegerRegisters	32
	nIL1CachetoCPUDataPathSize	8
	nIL1CachetoMemDataPathSize	128
	nIL1MemtoCacheDataPathSize	128
	nIL1CacheLines	256
	nIL1Associativity	8
	nDL1LineSize	128
	nDL1CachetoCPUDataPathSize	8
	nDL1CPUtoCacheDataPathSize	8
	nProg	8
	VERBOSE	false
	use_emulator	true
	HasAcceleratorPorts	false
******************************************/