/********************************* 
  Details for configuration 17448
 ********************************* 
 Module bus_multiqueue.sim
	nCPU	2
	nBufferSize	10
	nRequestWidth	32
	Snooping	false
 Module dram.sim
	nBanks	4
	nRows	2048
	nCols	512
	TRRD	60
	TRAS	150
	TRCD	60
	CL	60
	TRP	60
	TRC	210
	TREF	10000000
	nDataPathSize	32
	nCacheLineSize	32
	nCtrlQueueSize	8
	nProg	1
	Snooping	false
	VERBOSE	false
 Module .sim
	nCPUtoCacheDataPathSize	8
	nCachetoCPUDataPathSize	8
	nMemtoCacheDataPathSize	32
	nCachetoMemDataPathSize	32
	nLineSize	32
	nCacheLines	256
	nAssociativity	256
	nStages	1
	nDelay	1
	nProg	1
	nMSHR	8
	nMSHRRead	256
	nDCPTEntries	256
	nDCPTAssoc	1
	nDCPTNumOfDeltas	20
	nDCPTBitsOfDelta	8
 Module CpuPPC405.sim
	nIntegerRegisters	32
	nIL1CachetoCPUDataPathSize	8
	nIL1CachetoMemDataPathSize	32
	nIL1MemtoCacheDataPathSize	32
	nIL1CacheLines	256
	nIL1Associativity	2
	nDL1LineSize	32
	nDL1CachetoCPUDataPathSize	8
	nDL1CPUtoCacheDataPathSize	8
	nProg	8
	VERBOSE	false
	use_emulator	true
	HasAcceleratorPorts	false
******************************************/